
/******************************************************************************
*@file  : main.c
*@brief : main program
******************************************************************************/

#include "main.h" 
#include "app.h"   
#include "system_mpu_armv8m.h"   

#define CACHEABLE_FLASH_TEST
#define NON_CACHEABLE_FLASH_TEST    

#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
   
const struct mpu_armv8m_region_cfg_t region_cfg_init[] = {
           /*ROM Space, SPI Flash lower 512KB, cacheable, code*/  
           {
               0,
               0x00000000,
               0x0807FFFF, 
               MPU_ARMV8M_MAIR_ATTR_CODE_IDX, 
               MPU_ARMV8M_XN_EXEC_OK, 
               MPU_ARMV8M_AP_RW_PRIV_UNPRIV, 
               MPU_ARMV8M_SH_NONE,
           }, 
           /*SPI Flash upper 1536KB, non-cacheable, data*/  
           {
               1,
               0x08080000,
               0x081FFFFF, 
               MPU_ARMV8M_MAIR_ATTR_FDATANOCACHE_IDX, // flash data, non-cacheable     
               MPU_ARMV8M_XN_EXEC_NEVER,
               MPU_ARMV8M_AP_RW_PRIV_UNPRIV,  
               MPU_ARMV8M_SH_NONE,
           }, 
           /*SRAM lower 64KB, cacheable, data*/  
           {
               2,
               0x20000000,
               0x2000FFFF, 
               MPU_ARMV8M_MAIR_ATTR_DATA_IDX,   
               MPU_ARMV8M_XN_EXEC_OK, 
               MPU_ARMV8M_AP_RW_PRIV_UNPRIV, 
               MPU_ARMV8M_SH_NONE,
           }, 
           /*SRAM upper 64KB, non-cacheable, data*/  
           {
               3,
               0x20010000,
               0x2001FFFF,
               MPU_ARMV8M_MAIR_ATTR_DATANOCACHE_IDX,   // sram data, non-cacheable 
               MPU_ARMV8M_XN_EXEC_NEVER,
               MPU_ARMV8M_AP_RW_PRIV_UNPRIV,  
               MPU_ARMV8M_SH_NONE,
           }, 
           /*Device memory type*/          
           {
               4,
               0x40000000,
               0xFFFFFFFF, 
               MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX,
               MPU_ARMV8M_XN_EXEC_NEVER,
               MPU_ARMV8M_AP_RW_PRIV_UNPRIV,  
               MPU_ARMV8M_SH_NONE,
           }, 
};

static void mpu_init_cfg(void)
{
  struct mpu_armv8m_dev_t dev_mpu = { MPU_BASE };
  int32_t i;


    /* configure non secure MPU regions */
    for (i = 0; i < ARRAY_SIZE(region_cfg_init); i++)
    {
      if (system_mpu_armv8m_region_enable(&dev_mpu,
        (struct mpu_armv8m_region_cfg_t *)&region_cfg_init[i]) != MPU_ARMV8M_OK)
      {
        while(1); 
      }
    }

    /* enable non secure MPU */
    system_mpu_armv8m_enable(&dev_mpu, PRIVILEGED_DEFAULT_DISABLE, HARDFAULT_NMI_ENABLE);  

}

 
uint8_t TEST_txBuffer[256]; 
/******************************************************************************
*@brief : main program
*@param : none
*@return: none
******************************************************************************/
int main(void)
{
    uint32_t i;
    
	HAL_Init();  
    SystemClock_Config(SYSCLK_180M_SRC_RC64M, RCC_PCLK1_DIV_1, RCC_PCLK2_DIV_1);   
    
    BSP_UART_Init(UART1);  
    
    mpu_init_cfg();   
    
    HAL_Init_Ex();   
	
	printfS("\r\n\r\n");
	printfS("************************************************************\r\n\r\n");
    printfS("system startup\r\n");
	printfS("Firmware was created in %s %s \n", __DATE__, __TIME__);
	get_reset_source();
    BSP_MCO_Init(RCC_MCO_HCLK, 10);
    
	printfS("HCK: %u\r\n", HAL_RCC_GetHCLKFreq());
	printfS("PCLK1: %u\r\n", HAL_RCC_GetPCLK1Freq());
	printfS("PCLK2: %u\r\n", HAL_RCC_GetPCLK2Freq());
    printfS("\r\n");
	printfS("************************************************************\r\n\r\n");
	HAL_NORFLASH_Init(); 
    
    #ifdef CACHEABLE_FLASH_TEST
    HAL_NORFLASH_Erase(0x008000, 0x1000);     
    for(i = 0; i < 256;)
    {
        uint32_t value;         
        value = *(volatile uint32_t *)(0x08008000 + i); 
        printfS("value0: 0x%x\r\n", value);   
        i = i + 4;  
    }
    
    for(i = 0; i < 256; i++) 
    {
        TEST_txBuffer[i] = i;   
    }
    
    HAL_NORFLASH_Program(0x008000, TEST_txBuffer, 256); 
    for(i = 0; i < 256;)
    {
        uint32_t value;         
        value = *(volatile uint32_t *)(0x08008000 + i); 
        printfS("value1: 0x%x\r\n", value);   
        i = i + 4;  
    }
    #endif  
    
    #ifdef NON_CACHEABLE_FLASH_TEST   
    HAL_NORFLASH_Erase(0x0080000, 0x1000);     
    for(i = 0; i < 256;)
    {
        uint32_t value;         
        value = *(volatile uint32_t *)(0x08080000 + i); 
        printfS("value2: 0x%x\r\n", value);   
        i = i + 4;  
    }
    
    for(i = 0; i < 256; i++) 
    {
        TEST_txBuffer[i] = i;   
    }
    
    HAL_NORFLASH_Program(0x0080000, TEST_txBuffer, 256); 
    for(i = 0; i < 256;)
    {
        uint32_t value;         
        value = *(volatile uint32_t *)(0x08080000 + i); 
        printfS("value3: 0x%x\r\n", value);   
        i = i + 4;  
    }
    #endif  
    
    while(1)
    {
    
    }
}














